Hot swap safeguard circuit of ultra DMA hard disk

ABSTRACT

A hot swap circuit board and associated cable and connector arrangement for an ATA100 computer-disk drive interface is disclosed. The hot swap circuit board comprises a key-switched power supply control circuit with a simultaneously key-operated mechanical lock, a logic control circuit for READ and WRITE control signals and a set of logic switchable bi-directional impedance circuits with signal regeneration for the control and data signals across the ATA100 Interface. During normal operation, a security lock on the hot swap circuit board is kept in its locked position thus preventing any accidental disconnection of the ATA100 interface connector while simultaneously supplying electrical power and transmitted and regenerated control and data signals across the ATA100 interface. The unlocking mechanism is also disclosed.

FIELD OF THE INVENTION

[0001] This invention is related to, although not limited to, thecomputer-disk drive interface. More specifically, the invention isrelated to an electronic hardware for the hot swapping of individualdisk drives or disk arrays from a microcomputer.

BACKGROUND OF THE INVENTION

[0002] With the rapid development of micro-computers and associatedperipherals of higher performance at ever decreasing cost, operatingsystems with ever increasing functionality and reliability, numerousapplication software for easy creation of multi-media, content richinformation and the explosive advancement of the Internet infrastructurefor information delivery and sharing, micro-computer users now routinelydemand that their hard disk drives sustain a tremendous data transferrate while storing voluminous data. For example, one of the latestindustry standard definitions of the computer-disk drive Interface, orI/F, is called ATA100, and it specifies a data transfer rate of 100 MB/s(Megabyte/sec) through an 80 wire flat data cable. Additionally, thesehard disk drives must be quickly interchangeable with data securityfollowed by easy I/O in the course of data transfer. Since thetraditional practice for disk swapping of power cycling and rebooting ofthe micro-computer is still quite time consuming and prone to systemreliability problems, an emerging market requirement for the process ofdisk swapping is that the micro-computer power supply stay on throughoutthe process, or the so-called hot swapping of disk drive. With thistechnique, the hard disk drive can now be easily plugged into and pulledout of the drive rack. In other words, the hard disk drive now behavesmore like a removable hard disk.

[0003] As the speed of Central Processing Unit (CPU) of themicro-computer continues to increase without bound, the correspondingdata transfer rate between a single hard disk drive and the host adapterneeds to be improved to maintain the system data throughput. In fact,even at the data transfer rate of 100 MB/s, it is much too slow comparedto the speed of CPU and has become the data bottleneck of the computersystem. A natural solution for this problem is the deployment of diskarrays working in parallel to ease this data bottleneck. Consequently,the same market requirement of hot swapping also gets applied to thedisk array.

[0004] Therefore, a solution is needed to allow, with secured access,the hot swapping of individual hard disk drives and disk arrays from amicro-computer while maintaining an ATA100 data transfer rate of 100MB/s across the computer-disk drive interface, which is an industrystandard definition of the computer-disk drive interface.

SUMMARY OF THE INVENTION

[0005] The first objective of this invention is to devise a techniquethat allows the hot swapping of individual hard disk drives and diskarrays from a micro-computer, thus effectively making the hard diskdrive or disk array behave more like a removable hard disk or removabledisk array.

[0006] The second objective of this invention is to devise a techniquethat allows the hot swapping of individual hard disk drives and diskarrays from a micro-computer wherein the computer-disk drive interfaceis the industry standard ATA100.

[0007] The third objective of this invention is to devise a techniquethat allows the hot swapping of individual hard disk drives and diskarrays from a microcomputer with secured access.

[0008] Other objectives, together with the foregoing are attained in theexercise of the invention pursuant to the following description andresulting in the embodiment illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0009]FIG. 1A and FIG. 1B illustrate a system comprising a computer anda disk drive with the industry standard ATA100 interface wherein theinsertion of a simple switch is attempted for the purpose of hotswapping,

[0010]FIG. 2A and FIG. 2B illustrate a Power Supply Control Circuitsubsystem and its associated block diagram representation of the presentinvention for hot swapping;

[0011]FIG. 3A shows the detailed timing diagram of control signalsinvolved in the READ operation across the ATA100 Interface between acomputer and a disk drive;

[0012]FIG. 3B shows the detailed timing diagram of control signalsinvolved in the WRITE operation across the ATA100 Interface between acomputer and a disk drive;

[0013]FIG. 4A and FIG. 4B illustrate a Logic Control Circuit subsystemand its associated block diagram representation of the present inventionfor hot swapping;

[0014]FIG. 5A and FIG. 5B illustrate a Switchable Bi-directional SignalTransmission & Regeneration Circuit subsystem and its associated blockdiagram representation of the present invention for hot swapping;

[0015]FIG. 5C illustrates the application of the SwitchableBi-directional Signal Transmission & Regeneration Circuit subsystems tothe set of control signals involved in the READ and WRITE operationacross the ATA100 Interface between a computer and a disk drive;

[0016]FIG. 5D is the same illustration as shown in FIG. 5C except thatthe various Switchable Bi-directional Signal Transmission & RegenerationCircuit subsystems from FIG. 5C are condensed into one functional blockrepresentation for simplicity; and

[0017]FIG. 6A through FIG. 6F illustrate a sequence of progressiveoverviews of the present invention in a complete environment of systemhook up with a computer and a disk drive while going through an entirecycle of hot swapping operation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0018]FIG. 1A illustrates a system comprising a computer and a diskdrive with the industry standard ATA100 interface. A Computer 1 iscommunicatively connected to a Hard Disk Drive 2 with an ATA100Interface Cable 3 that is an 80 pin flat cable. With a data transferrate between the Computer 1 and the Hard Disk Drive 2 of 100 MB/s, thefrequency of the corresponding data carrier signal of the ATA100 I/F canbe up to 50 MHz within a period of Direct Memory Access, or DMA. Duringthe course of signal transfer with such a high frequency, there will beunintended disturbance to the carrier signal due to naturalelectromagnetic radiation. In fact, this unintended electromagneticradiation disturbance is the main cause of data transfer error betweenthe Computer 1 and the Hard Disk Drive 2. Another cause of data transfererror is the unintended disturbance to the carrier signal as a result ofthe coupling of neighboring electromagnetic fields from the parallelsignal wires within the ATA100 Interface Cable 3. Nevertheless,regardless of the cause of data transfer error, in general the longerthe length of the ATA100 Interface Cable 3 the more the net datatransfer error rate will be from these disturbances. Thus, for anacceptable data transfer error rate, the maximum length of the ATA100Interface Cable 3 has been limited to 45cm as indicated.

[0019]FIG. 1B illustrates a system comprising a computer and a diskdrive with the industry standard ATA100 interface wherein the insertionof a simple switch is attempted for the purpose of hot swapping. Noticethat, while the ATA100Interface Cable 3 remains the same as in FIG. 1A,a Simple Switch Printed Circuit Board 4 and an associated Cable for Hotswapping 5 must be added. For easy mechanical access, disconnecting andconnecting the Hard Disk Drive 2 throughout the swapping operation, aminimum length of about 10 cm is required of the Cable for Hot swapping5. This means that, with the insertion of a simple switch, the effectivelength of the interface cable between the Computer 1 and the Hard DiskDrive 2 is increased to about 55 cm, significantly beyond the limit of45cm for reliable data transfer. Given the explanation before, theconsequence is a degraded and unacceptable data transfer error rate froma combination of excessive signal attenuation, electromagnetic radiationand coupling of electromagnetic fields between neighboring signal wires.In essence, this is why there has not been any simple prior art circuitfor the hot swapping of hard disk with an ATA100 interface.

[0020] In order to overcome the technical difficulties as explainedabove, the present invention consists of a number of keyelectromechanical subsystems. These are a Power Supply Control Circuit,or PSCC; a Logic Control Circuit, or LCC; and a number of SwitchableBi-directional Signal Transmission & Regeneration Circuit, or SBDSTR.

[0021]FIG. 2A illustrates the Power Supply Control Circuit 8. From theright hand side, two incoming power supplies +12V Power Supply 10 and+5V Power Supply 11 are switched with a Triple Pole Single Throw, orTPST Switch 13. The TPST Switch 13 is operated through a Security Lock12. The corresponding switched power supplies on the left hand side arecalled Key Switched +12V Power Supply 14 and Key Switched +5V PowerSupply 15. To avoid any switching related surge of electrical current orarcing, a type of solid state switch should be used for the TPST Switch13. Additionally, another concurrently switched 5 Volt level logicsignal, called Security Logic Signal SW 17, is also generated through anarrangement with a Pull Down Resistor 16. Furthermore, the Security Lock12 is also shown to simultaneously operate a Mechanical Lock for ATA100Computer Side Connector 125 between an “Unlocked” state and a “Locked”state. More detailed explanation of the Mechanical Lock for ATA100Computer Side Connector 125 will be given later. Thus, by tracing thelogic implication of each of the two states of “Security Lock Open” and“Security Lock Close” of the Security Lock 12 from FIG. 2A, a functionalblock diagram representation, as shown in FIG. 2B, of the Power SupplyControl Circuit 8 and its associated logic states, as shown in TABLE 1,for the various output power supplies and signals are obtained.

[0022] For example, with the “Security Lock 12 open”, the TPST Switch 13is “Open”, the Mechanical Lock for ATA100 Computer Side Connector 125 is“Unlocked” and the Security Logic Signal SW 17 is “Logic Low (0)”; andwith “Security Lock 12 Close”, the TPST Switch 13 is “Close”, theMechanical Lock for ATA100 Computer Side Connector 125 is “Locked” andthe Security Logic Signal SW 17 is “Logic High (1)”, etc. In addition,for simplicity of explanation later, notice the usage of respectivegraphical symbols to represent the two states of the Mechanical Lock forATA100 Computer Side Connector 125.

[0023]FIG. 3A shows the detailed timing diagram of control signalsinvolved in the READ operation across the ATA100 Interface between acomputer and a disk drive. The control signals are, as defined by theATA100 Interface, DACK_, IOW_, IOR_ and IORDY. The associated datasignal to be read from the Hard Disk Drive 2 by the Computer 1 is DATA.At time to all the control signals are high signifying an inactive stateof the ATA100 Interface. TABLE 1 Security Lock Position Action &Security Lock Security Lock Output Open Close TPST Switch Open Close KeySwitched Not Powered Powered +12 V Supply Key Switched Not PoweredPowered +5 V Supply Mechanical Lock for ATA100 Computer Side Connector

Security Logic Logic Low Logic High Signal SW (0) (1)

[0024] At time t₁ the signal DACK_ drops to LOW setting the stage forthe ATA100 Interface to become active. At time t₂ both IOW_ and IOR_drop to LOW while IORDY stays HIGH. This event transitions the ATA100Interface into an active READ state. Thus, following the next downtransition of IORDY at time t₃ and up transition at times t₄ and t₅, theATA100 Interface expects a sequence of valid DATA signal from the HardDisk Drive 2 corresponding to the times while IORDY is HIGH. These timeintervals are marked as “READ DATA VALID”, etc. afterwards, this READoperation is terminated with an ordered up transition of the signalsIOW_, IOR_ and IORDY around time t₆. Finally, the ATA100 Interface isreturned to its inactive state with the up transition of DACK_ at timet₇.

[0025]FIG. 3B shows the detailed timing diagram of control signalsinvolved in the WRITE operation across the ATA100 Interface between acomputer and a disk drive. Here, except for the reversal of rolesbetween the signals IOR_ and IORDY, the timing sequence is the same asthat of the READ operation from FIG. 3A.

[0026] Based upon the aforementioned timing diagram of control signalsinvolved in the READ and WRITE operation across the ATA100 Interfacebetween a computer and a disk drive, a Logic Control Circuit 18 isdevised and is illustrated in FIG. 4A. The Logic Control Circuit 18consists of a set of interconnected 4-input NOR Gate U1, a 3-input NORGate U2, a OR Gate U3OR Gate U3 and a Inverter U4 with the followinginput and output signals:

[0027] Input:

[0028] Security Logic Signal SW 17, Computer Side ATA100 I/F SignalDACK_ 20,

[0029] Computer Side ATA100 I/F Signal IOR_ 21, Computer Side ATA100 I/FSignal

[0030] IOW_ 22, Computer Side ATA100 I/F Signal IORDY 23

[0031] Output:

[0032] READ Command Signal UDMAR 24, WRITE Command Signal UDMAW 25

[0033] The corresponding functional block diagram representation ofLogic Control Circuit 18 is shown in FIG. 4B. Tracing the logicimplication of a number of relevant combination of logic inputs, TABLE 2is obtained that maps the respective combination of logic inputs totheir corresponding output logic states. For example:

[0034] Input:

[0035] SW=0 (LOW), DACK_=DON'T CARE, IOR_=DON'T CARE, IOW_=DON'T CARE,IORDY=DON'T CARE

[0036] Output:

[0037] UDMAR=0 (LOW), UDMAW=0 (LOW) as “SW=0”causes the output ofInverter U4 to be “1” and this causes the output of OR Gate U3 to be “1”and this causes the output of both the 4-input NOR Gate U1 and the3-input NOR Gate U2 to be “0”.

[0038] For another example:

[0039] Input:

[0040] SW=1 (HIGH), DACK_(—)=0 (LOW), IOR_(—)=0 (LOW), IOW₁₃ =0 (LOW),IORDY=Transition from 0 (LOW) to 1 (HIGH).

[0041] Output:

[0042] UDMAW=0 (LOW), as “IORDY=Transition from 0 (LOW) to 1 (HIGH)”causes the output of the 3-input NOR Gate U2 to be “0”.

[0043] UDMAR=1 (HIGH), as “SW=1” causes the output of Inverter U4 to be“0” and this, in combination with DACK_(—)=0, causes the output of ORGate U3 to be “0”. Given that the output of 3-input NOR Gate U2 is “0”from above, the fact that IOW_(—)=0 and IOR_(—)=0 then causes the outputof the 4-input NOR Gate U1 to be “1”, etc. TABLE 2 Logic Input “X” means“DON'T CARE” Logic State SW DACK_(—) IOR_(—) IOW_(—) IORDY State-I 0 X XX X UDMAR = 0, UDMAW = 0 State-II 1 1 X X X UDMAR = 0, UDMAW = 0State-III 1 0 0 0

UDMAR = 1, UDMAW = 0 State-IV 1 0

0 0 UDMAR = 0, UDMAW =1

[0044] Now if one combines the various logic input states from thedetailed timing diagram of control signals from FIG. 3A with thefunctionality of the Logic Control Circuit 18, one would obtain TABLE 3that maps the various time points in the READ operation across theATA100 Interface to their corresponding output logic states. Forexample, at time=t_(o), the following output state is obtained:

[0045] UDMAR=0, UDMAW=0 which means NO READ activity and NO WRITEactivity.

[0046] However, for another example, at time=t₅ , the following outputstate is obtained:

[0047] UDMAR=1, UDMAW=0 which means active READ operation but NO WRITEactivity, etc. TABLE 3 GIVEN: SW = 1 Logic State Time Point IOR_(—)IOW_(—) IORDY UDMAR UDMAW t₀ 1 1 1 0 0 t₁ 1 1 1 0 0 t₂ 0 0 1 1 0 t₃ 0 00 1 0 t₄ 0 0 0 1 0 t₅ 0 0 1 1 0 t₆ 1 1 1 0 0 t₇ 1 1 1 0 0

[0048] Similarly, although not shown, if one combines the various logicinput states from the detailed timing diagram of control signals fromFIG. 3B with the functionality of the Logic Control Circuit 18, onewould obtain another table that maps the various time points in theWRITE operation across the ATA100 Interface to their correspondingoutput logic states.

[0049]FIG. 5A and FIG. 5B illustrate a SBDSTR subsystem 38 and itsassociated functional block diagram representation. FIG. 5A shows thedetailed circuitry of the SBDSTR subsystem 38 whose logic control inputsare READ Command Signal UDMAR 24 and WRITE Command Signal UDMAW 25. Thecontrolled, bi-directional signals are Computer Side Data Signal 30 andDisk Side Data Signal 31. Functionally, the blocks U5, U7, U8 and U10are Logic Switchable Impedance symbolized by “Z_(r)”. That is:

[0050] When input=0, Z_(r)=High Impedance blocking signal transmissionthrough; and

[0051] When input=1, Z_(r)=Low Impedance allowing signal transmissionthrough without significant attenuation.

[0052] The function of the analog blocks U6 and U9 are SignalRegeneration and Amplification that takes an attenuated input signal,and regenerates and amplifies it to its original unattenuated level.

[0053] Combining two logic input states of the READ Command Signal UDMAR24 and the WRITE Command Signal UDMAW 25 with the describedfunctionality of the SBDSTR subsystem 38, one would obtain another tablethat maps the logic input states to their corresponding functionality.This is shown as TABLE 4. For example,

[0054] When READ Command Signal UDMAR 24=1 and WRITE Command SignalUDMAW 25=0,

[0055] Z_(r) of both U5 and U7=Low Impedance allowing signaltransmission through without significant attenuation; while

[0056] Z_(r) of both U8 and U10=High Impedance blocking signaltransmission through.

[0057] Thus, the Disk Side Data Signal 31 is allowed to be transmitted,with regeneration and amplification by the Signal Regeneration AmplifierU6, from the left hand side to the right hand side of the SBDSTRsubsystem 38 to become the Computer Side Data Signal 30 while thereverse transmission of signal, from the right hand side to the lefthand side, is completely blocked, etc. The corresponding table of logicand functionality is shown in TABLE 4. TABLE 4 UDMAR = 1 UDMAW = 0Signal Transmission from High Impedance with CSDS to DSDS No SignalTransmission Signal Transmission from Low Impedance with DSDS to CSDSSignal Regeneration UDMAR = 0 UDMAW = 1 Signal Transmission from LowImpedance with CSDS to DSDS Signal Regeneration Signal Transmission fromHigh Impedance with DSDS to CSDS No Signal Transmission

[0058] With the functionality of the SBDSTR understood, FIG. 5Cillustrates the application of four (4) of the SBDSTR subsystems to theset of control signals involved in the READ and WRITE operation acrossthe ATA100 Interface between a computer and a disk drive. While the rawlogic input signals are common to the four SBDSTR subsystems, namely,READ Command Signal UDMAR 24 and WRITE Command Signal UDMAW 25, thetransmission signals under control are all different. They are asfollows: as illustrated in left hand as illustrated in right hand sideof FIG. 5C side of FIG. 5C SBDSTR_(A) Drive Side ATA100 I/F SignalComputer Side ATA100 I/F Signal DACK_200 DACK_20 SBDSTR_(B) Drive SideATA100 I/F Signal Computer Side ATA100 I/F Signal IOR_210 IOR_21SBDSTR_(C) Drive Side ATA100 I/F Signal Computer Side ATA100 I/F SignalIOW_220 IOW_22 SBDSTR_(D) Drive Side ATA100 I/F Signal Computer SideATA100 I/F Signal IORDY 230 IORDY 23

[0059] Additionally, all the “UDMAR” logic inputs to the four SBDSTRsubsystems are grounded, or set to logic “0” while all the “UDMAW” logicinputs to the four SBDSTR subsystems are driven by an OR Gate U12 whoseinputs are READ Command Signal UDMAR 24 and WRITE Command Signal UDMAW25. In this way, whenever the logic state needs to be in an active READor WRITE operation across the ATA100 Interface, that is:

[0060] Either (UDMAR=1, UDMAW=0)

[0061] Or (UDMAR=0, UDMAW=1),

[0062] all the above control signals from the “right hand side” will beallowed to pass through to the “left hand side” with low impedancewithout significant attenuation, as required. To simplify theexplanation of the hot swapping system, the various SBDSTR subsystemsfrom FIG. 5C are further condensed into one functional blockrepresentation in FIG. 5D, called SBDSTR_(O) 380.

[0063] With all the key subsystems PSCC, LCC and SBDSTR of the presentinvention described above, FIG. 6A through FIG. 6F illustrate a sequenceof progressive overviews of the present invention in a completeenvironment of system hook up with a computer and a disk drive whilegoing through an entire cycle of hot swapping operation.

[0064] In FIG. 6A, a Hot Swap Printed Circuit Board 40 of the presentinvention is shown connected to a Hard Disk Drive 2 on the left handside via a cable for hot swapping 5. On its right hand side, the HotSwap Printed Circuit Board 40 is connected to a Computer 1 via a ATA100Interface Cable 3 that is an 80 pin flat cable. For the purpose of hotswapping, it is necessary that the connection between the Hot SwapPrinted Circuit Board 40 and the ATA100 Interface Cable 3 be madethrough a disengageable connector. Furthermore, a Mechanical Lock forATA100 Computer Side Connector 125 is provided on the Power SupplyControl Circuit 8 of the Hot Swap Printed Circuit Board 40. As shown,the Mechanical Lock for ATA100 Computer Side Connector 125 is in its“Locked” position thus preventing the disengagement of the connectionbetween the Hot Swap Printed Circuit Board 40 and the ATA100 InterfaceCable 3. The Hot Swap Printed Circuit Board 40 consists of a PowerSupply Control Circuit 8, a Logic Control Circuit 18, an SBDSTR₀ 380 anda number, “n”, of SBDSTR. The SBDSTR are labeled SBDSTR₁ 381, SBDSTR₂382, . . . and SBDSTR_(n) 390. The number “n” is equal to the totalnumber of data signal wires, as defined by the ATA100 Interfacestandard, required for the communication between the Computer 1 and theHard Disk Drive 2. Finally, a set of System Ground Wiring 500 isprovided for all the subsystems of the Hot Swap Printed Circuit Board 40and among the Hot Swap Printed Circuit Board 40, the Hard Disk Drive 2and the Computer 1. The ATA100 transmission data signals under controlare as follows: as illustrated at the as illustrated at the left handside FIG. 6A right hand side FIG. 6A SBDSTR₁ DSDS Number One 311 CSDSNumber One 301 SBDSTR₂ DSDS Number Two 312 CSDS Number Two 302SBDSTR_(n) DSDS Number n 320 CSDS Number n 310

[0065] As before, the logic input signals for all the SBDSTR are theREAD Command Signal UDMAR 24 and the WRITE Command Signal UDMAW 25. Inturn, the READ Command Signal UDMAR 24 and the WRITE Command SignalUDMAW 25 come from the Logic Control Circuit 18 whose input signalSecurity Logic Signal SW 17 is driven by the Power Supply ControlCircuit 8. As illustrated, the Security Lock of the Power Supply ControlCircuit 8 is closed. Furthermore, as indicated by NOTE-A and the LogicState of the Logic Control Circuit 18, State-III or State-IV, thecombination of signals Computer Side ATA100 I/F Signal DACK_ 20,Computer Side ATA100 I/F Signal IOR_ 21, Computer Side ATA100 I/F SignalIOW_ 22 and Computer Side ATA100 I/F Signal IORDY 23 puts the Hot SwapPrinted Circuit Board 40 in either one of the following states:

[0066] (A) READ Command Signal UDMAR 24=1 and WRITE Command Signal UDMAW25=0, or a READ operation through the ATA100 Interface; or

[0067] (B) READ Command Signal UDMAR 24=0 and WRITE Command Signal UDMAW25=1, or a WRITE operation through the ATA100 Interface.

[0068] Since the Security Lock of the Power Supply Control Circuit 8 isclosed, both the Key Switched +12V Power Supply 14 and the Key Switched+5V Power Supply 15 are powered respectively by the +12V Power Supply 10and the +5V Power Supply 11 (refer to TABLE 1). In turn, the KeySwitched +12V Power Supply 14 and the Key Switched +5V Power Supply 15would provide the needed power for the Hard Disk Drive 2. Since theMechanical Lock for ATA100 Computer Side Connector 125 is in its“Locked” position, it would prevent any unauthorized tampering oraccidental interruption of the connection between the Computer 1 and theHard Disk Drive 2 from happening while the system is actively performingits READ or WRITE operation. Otherwise, such tampering or interruptioncould easily result in loss of data and/or damage to the operatingelectronic circuitry.

[0069] For the purposes of illustration, an example having the followinglogic state is provided:

[0070] (A) READ Command Signal UDMAR 24=1 and WRITE Command Signal UDMAW25=0, or a READ operation through the ATA100 Interface.

[0071] From TABLE 4 it can be seen that all signal transmission from theside of the Hard Disk Drive 2, through an SBDSTR, to the side of theComputer 1 will only encounter low impedance with signal regeneration.Meanwhile, all signal transmission from the side of the Computer 1,through an SBDSTR, to the side of the Hard Disk Drive 2 will encounterhigh impedance, and thus will be blocked. Furthermore, while the totaldistance of travel by the respective data signals is, as before, stillincreased from 45 cm to about 55 cm, the function of signal regenerationby the SBDSTR acts to compensate for the additional signal attenuationand to restore the required quality of the data signals for the fullATA100 Interface data rate of 100 MB/sec.

[0072] Applying the reasoning process similar to the above, it shouldbecome clear by now that the other example having the alternative logicstate:

[0073] (B) READ Command Signal UDMAR 24=0 and WRITE Command Signal UDMAW25=1, or a WRITE operation through the ATA100 Interface.

[0074] As illustrated, it will cause all signal transmission from theside of the Computer 1, through an SBDSTR, to the side of the Hard DiskDrive 2 to only encounter low impedance with signal regeneration thusalso capable of operating at the full ATA100 Interface data rate of 100MB/sec.

[0075] Next, FIG. 6B illustrates the present invention wherein theSecurity Lock is opened up, for example, by an authorized operator, inpreparation for a hot swapping operation. Both the Key Switched +12VPower Supply 14 and the Key Switched +5V Power Supply 15 are nowswitched into a “Not Powered” state accordingly to TABLE 1. This isimportant for the safeguard of the system. Otherwise a subsequent act ofdisconnection could cause the flow of an instantaneous interferingcurrent or an arcing through the power supplies thus damaging theelectronic hardware and/or software of the system. Also, the SecurityLogic Signal SW 17 is reset to Logic Low (0) per TABLE 1. This causes,per TABLE 2 for Logic Control Circuit 18, the following to happen:

[0076] READ Command Signal UDMAR 24=0 and

[0077] WRITE Command Signal UDMAW 25=0.

[0078] In turn, the above switches all the SBDSTR into the followingstate (TABLE 4):

[0079] SBDSTR₀ 380: High Impedance with No Signal Transmission

[0080] SBDSTR₁ 381: High Impedance with No Signal Transmission

[0081] SBDSTR₂ 382: High Impedance with No Signal TransmissionSBDSTR_(n) 390: High Impedance with No Signal Transmission

[0082] In essence, all of the right hand signals:

[0083] Computer Side ATA100 I/F Signal DACK_ 20,

[0084] Computer Side ATA100 I/F Signal IOR_ 21,

[0085] Computer Side ATA100 I/F Signal IOW_ 22,

[0086] Computer Side ATA100 I/F Signal IORDY 23,

[0087] CSDS Number One 301,

[0088] CSDS Number Two 302, and

[0089] CSDS Number n 310

[0090] are electrically isolated from their corresponding left handsignals:

[0091] Drive Side ATA100 I/F Signal DACK_ 200,

[0092] Drive Side ATA100 I/F Signal IOR_ 210,

[0093] Drive Side ATA100 I/F Signal IOW_ 220,

[0094] Drive Side ATA100 I/F Signal IORDY 230,

[0095] DSDS Number One 311,

[0096] DSDS Number Two 312, and

[0097] DSDS Number n 320.

[0098] This is also important for the safeguard of the system. Otherwisea subsequent act of disconnection could cause the flow of aninstantaneous interfering current or an arcing through the respectivesignal paths thus damaging the electronic hardware and/or software ofthe system. At this time, the Mechanical Lock for ATA100 Computer SideConnector 125 is also “Unlocked” (TABLE 1) allowing safe physicaldisconnection of the Hard Disk Drive 2 from the Computer 1. This actionis illustrated in FIG. 6C with a set of two thick, horizontal arrowsseparating the group of

[0099] Hard Disk Drive 2, Cable for Hot swapping 5 and Hot Swap PrintedCircuit Board 40

[0100] From the group of

[0101] Computer 1 and ATA100 Interface Cable 3. Notice the graphicallysymbolized “Unlocked” state of the Mechanical Lock for ATA100 ComputerSide Connector 125.

[0102]FIG. 6D illustrates the first step of reconnection of the abovetwo groups with another set of two thick, horizontal arrows. Noticeagain the graphically symbolized “Unlocked” state of the Mechanical Lockfor ATA100 Computer Side Connector 125 and the state of Security Lock12=Open. As all the switched power supplies, control and data signalsare still either “Not Powered” or “totally isolated between the lefthand side and the right hand side”, the act of reconnection isguaranteed to be free of any risk of system damage.

[0103]FIG. 6E illustrates the second step of reconnection of the abovetwo groups wherein the Security Lock of the Power Supply Control Circuit8 is “Closed”, for example, by an authorized operator. Simultaneously,the Security Logic Signal SW 17 is set to Logic High (1) and theMechanical Lock for ATA100 Computer Side Connector 125 is switched intoits “Locked” position as graphically symbolized. Thus, the Key Switched+12V Power Supply 14 and the Key Switched +5V Power Supply 15 are now“powered” (TABLE 1) under the protection of the “Locked” Mechanical Lockfor ATA100 Computer Side Connector 125. Furthermore, the logic state ofthe Logic Control Circuit 18 is switched into State-II (TABLE 2), readyto be further switched into its subsequent normal operating states.

[0104]FIG. 6F illustrates the third step of reconnection of the abovetwo groups wherein the ATA100 Interface is switched back to its normaloperating state of READ or WRITE by the proper timing of the followingcontrol signals:

[0105] Computer Side ATA100 I/F Signal DACK_ 20,

[0106] Computer Side ATA100 I/F Signal IOR_ 21,

[0107] Computer Side ATA100 I/F Signal IOW_ 22, and

[0108] Computer Side ATA100 I/F Signal IORDY 23 (State-III or State-IVof TABLE 2, [t₂, t₃, t₄ , t₅ ] of TABLE 3).

[0109] Notice that, except for some minor differences in labeling, allthe functional characteristics of FIG. 6F are identical to those of FIG.6A. An important remark related to the employment of a manually operatedSecurity Lock 12 (FIG. 2A) by the Hot Swap Printed Circuit Board 40 isthat it satisfies the requirements of disk array RAID 1, an industrystandard which defines mirroring operation of hard disk drives.Specifically, in the course of mirroring operation of two hard diskdrives, the operating computer software and the startup of any specialsoftware for the hard disk drive are not allowed to stop running. Infact, in this case, only the startup by a manual switch is allowed toeffect the manipulation of hot swapping of hard disk drives.

[0110] Therefore, the illustrated embodiments of the present inventionfunction to insure a safe and secured hot swapping system of datacommunication between a Computer and a Hard Disk Drive while maintainingthe full ATA100 Interface data rate of 100 MB/sec and satisfying therequirements of the RAID industry standard for disk array. The inventionhas been described using exemplary preferred embodiments. However, forthose skilled in the art, the preferred embodiments can be easilyadapted and modified to suit additional applications without departingfrom the spirit and scope of this invention. Thus, it is to beunderstood that the scope of the invention is not limited to thedisclosed embodiments. On the contrary, it is intended to cover variousmodifications and similar arrangements based upon the same operatingprinciple. The scope of the claims, therefore, should be accorded thebroadest interpretations so as to encompass all such modifications andsimilar arrangements.

I claim:
 1. A hot swap circuit board adaptable for a computer-disk driveinterface of a computer-disk drive system, comprising: a key-switchedpower supply control circuit to provide power supply and a securitylogic signal, a set of logic switchable impedance circuits to provide aset of computer-supplied control signals; a logic control circuit toprovide a READ command signal and a WRITE command signal in response tothe security logic signal and the set of computer-supplied controlsignals; and a number of logic switchable bi-directional impedancecircuits corresponding to a number of data signals defined in thecomputer-disk drive interface; whereby the hot swap circuit boardperforms a function of safe hot swapping of a disk drive attached to thecomputer-disk drive interface without having to cycle the power of thecomputer-disk drive system while satisfying a requirement of diskmirroring operation wherein an operating computer software can not beinterrupted and no special software can be started.
 2. The hot swapcircuit board according to claim 1 wherein the set of logic switchableimpedance circuits further comprises a signal regeneration amplifier. 3.The hot swap circuit board according to claim 2 wherein thecomputer-disk drive interface further comprises a signal regenerationamplifier.
 4. The hot swap circuit board according to claim 3 whereinthe computer-disk drive system further comprises a cable with anincreased effective total cable length connecting thereof to maintain aspecified data rate of the computer-disk drive interface.
 5. The hotswap circuit board according to claim 4 wherein the hot swap circuitboard further comprises a mixed signal application circuit for itscircuitry to provide an additional advantage of reduction in cost,product size and power consumption.
 6. The hot swap circuit boardaccording to claim 1 wherein the key-switched power supply controlcircuit is a key-switched +12V power supply or a key-switched +5V powersupply.
 7. The hot swap circuit board according to claim 1 wherein thecomputer-disk drive interface is an ATA100 interface.
 8. The hot swapcircuit board according to claim 1 further comprises a security lock onthe hot swap circuit board so as to prevent any accidental disconnectionof the connector for the computer-disk drive interface whilesimultaneously supplying electrical power and transmitting signalsacross the computer-disk drive interface for normal operation.
 9. A hotswap circuit board adaptable for performing a function of safe hotswapping of a disk drive attached to an electrical interface between twoelectronic system, comprising: a key-switched power supply controlcircuit to provide power supply and a security logic signal; a set oflogic switchable impedance circuits to provide a set of control signalssupplied by the first electronic system; a logic control circuit toprovide a READ command signal and a WRITE command signal in response tothe security logic signal and the set of control signals supplied by thefirst electronic system; and a number of logic switchable bi-directionalimpedance circuits corresponding to a number of data signals defined inthe electric interface; whereby the function of safe hot swapping of thedisk drive is performed without having to cycle the power of the secondelectronic system while satisfying a requirement of disk mirroringoperation so as not to interrupt any functions then in operation by thefirst electronic system.
 10. A method for safe hot swapping of a diskdrive attached to a disk drive interface without having to cycle thepower of a computer-disk drive system while maintaining a specified datarate of the computer-disk drive interface across an increased effectivetotal cable length between the computer and the disk drive, comprising:providing a hot swap circuit board to the computer; providing a securitylock on the hot swap circuit board in its locked position so as toprevent any accidental disconnection of the disk drive interface whilesimultaneously supplying electrical power and transmitted andregenerated control signals and data signals across the disk driveinterface for normal operation; unlocking the security lock on the hotswap circuit board so as to enable a future disconnection of the diskdrive interface while simultaneously switching off the supply ofelectrical power and cutting off the transmission and the regenerationof control signals and data signals across the disk drive interface thusenabling the disconnection of the disk drive interface; removing thedisconnected disk drive interface and replacing it with a new diskdrive; and locking the security lock on the hot swap circuit board forthe new disk drive so as to prevent any accidental disconnection of thedisk drive interface while simultaneously resuming the supply ofelectrical power and the transmission and the regeneration of controlsignals and data signals across the disk drive interface for a resumednormal operation.
 11. The method for safe hot swapping of a disk driveaccording to claim 10 wherein the hot swap circuit board furthercomprises a key-switched power supply control circuit to provide powersupply and a security logic signal.
 12. The method for safe hot swappingof a disk drive according to claim 10 wherein the hot swap circuit boardfurther comprises a set of logic switchable impedance circuits toprovide a set of computer-supplied control signals.
 13. The method forsafe hot swapping of a disk drive according to claim 10 wherein the hotswap circuit board further comprises a logic control circuit to providea READ command signal and a WRITE command signal in response to thesecurity logic signal and the set of computer-supplied control signals.14. The method for safe hot swapping of a disk drive according to claim10 wherein the hot swap circuit board further comprises a number oflogic switchable bi-directional impedance circuits corresponding to anumber of data signals defined in the disk drive interface.
 15. Themethod for safe hot swapping of a disk drive according to claim 10wherein the disk drive interface is an ATA100 interface.